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Clocked S-R Flip Flop

Clocked S-R Flip Flop

Clocked S-R Flip Flop

  • a clocked S-R flip flop is designed by adding two AND gates to a basic NOR Gate flip flop.It is designed using four NAND gates.
  • excitation table of S-R flip flop
  • logic diagram of S-R fliop flop
  • A clock pulse(CP) is given to the inputs of the AND Gate.When the value of the clock pulse is '0',the outputs of both the AND Gates remain'0'. As soon as a pulse is given the value of CP turns '1'. This makes the values at S and R to pass through the NOR gate flip flop. But when the values of both S and R values turn '1', The HIGH values of CP causes both of them to turn to '0' for a short moment. As soon as the pulse is removed, the flip flop state becomes intermediate. Thus either of the two states may be caused, and it depends on whether the set or reset input of the flip-flop remains a '1' longer than the transition to '0' at the end of the pulse. Thus the invalid states can be eliminated.

    • logic Diagram of SR flip flop using NAND gates

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