R-S Latch

• Latchs is a basic building element in sequential circuits. Latches do not have clock signal, that is, they are asynchronous sequential circuits
• Latches are made up of static gates and are bi-stable i.e. it has two stable states and can switch between these states. Latches will have a feedback path from the output. Thus they change their output at any instant using the previous and present states of the signals

R-S latch bloack diagram


Where S=SET Input R=RESET Input Q=Output Qbar=Complemented Output
• RS latchimplemented using NOR gates and we can store either a 0 ar a 1 in this circuit depending upon the vlaue of R and S

1. When R=0, S=0 we don't have a change in the output in the circuit. Hence Q and Qbar remains in the previous state
2. When R=0, S= 1 we have ouput as Q=1 and Qbar=0. This as SET state.
3. When R=1, S=0 we have the output Q = 0, Qbar= 1. This state is called as reset state.
4. When R=1 and S=1, both R and S make outputs of their NOR gates 0. Hence we have Q=0, and Qbar= 0 which is not a valid case as Q&Qbar should be compliment of each other and hence we don't consider this case. This is called RACE CONDITION

• All these cases can be collactively represented in the truth table above